This invention relates to technology for removing unwanted metal from semiconductor wafers. More particularly, it pertains to methods for removing unwanted metal, particularly metal in the edge bevel region, using liquid etchants, as well as apparatus modules for performing such removal.
Damascene processing is a method for forming metal lines on integrated circuits. It is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. In Damascene processing, as well as other integrated circuit manufacturing processes, the conductive routes on the surface of the circuit are generally formed out of a common metal, traditionally aluminum. Copper is now a favored metal because of its higher conductivity and electromigration resistance when compared to aluminum, but copper presents special challenges because it readily diffuses into silicon oxide and reduces its electrical resistance at very low doping levels. During integrated circuit fabrication, the conductive metal is needed on the active circuit region of the wafer, i.e., the main interior region on the front side, but is undesirable elsewhere.
In a typical copper Damascene process, the formation of the desired conductive routes generally begins with a thin physical vapor deposition (PVD) of seed metal, followed by a thicker electrofill layer (which is formed by electroplating). The PVD process is typically sputtering. In order to maximize the size of the useable wafer area (sometimes referred to herein as the “active surface region”) and thereby maximize the number of integrated circuits produced per wafer), the electrofilled metal must be deposited to very near the edge of the semiconductor wafer. Thus, it is necessary to allow physical vapor deposition of the metal over the entire front side of the wafer. As a byproduct of this process step, PVD metal typically coats the front edge area outside the active circuit region, as well as the side edge, and to some degree, the backside.
Electrofill of the metal is much easier to control, since the electroplating apparatus can be designed to exclude the electroplating solution from undesired areas such as the edge and backside of the wafer. One example of plating apparatus that constrains electroplating solution to the wafer active surface is the SABRE™ clamshell electroplating apparatus available from Novellus Systems, Inc. of San Jose, Calif. and described in U.S. Pat. No. 6,156,167 “CLAMSHELL APPARATUS FOR ELECTROCHEMICALLY TREATING SEMICONDUCTOR WAFERS,” by E. Patton et al., and filed Nov. 13, 1997, which is herein incorporated by reference in its entirety. However, even with such advanced apparatus, small amounts of copper can be deposited on the edge regions of the wafer. Also, it is sometime desirable to remove material that was previously within (at smaller radii) the clamshell plating-exclusion region because the transition region may contain defects (e.g. particles, unplated areas, etc), or have a rapidly changing thickness profile, both of which may complicate subsequent copper planarization and/or removal operations for the wafer as a whole (e.g., CMP, ECMP (electrochemical mechanical polishing), MMEP (membrane mediated electropolishing), etc.).
The PVD metal remaining on the wafer edge after electrofill is undesirable for various reasons. One reason is that PVD metal layers left at the edge after CMP are not suitable for subsequent layer metal deposition on top of them (e.g. subsequent dielectric layer will not adhere well to the PVD copper base layer if it is not removed). Also, the PVD layers are thin and tend to flake off during subsequent handling, thus generating undesirable particles. This can be understood as follows. At the front side edge of the wafer, the wafer surface is beveled. Here the PVD layers are not only thin, but also unevenly deposited. Thus, they do not adhere well. Adhesion of subsequent dielectric layers onto such thin metal is also poor, thus introducing the possibility of even more particle generation. By contrast the PVD metal on the active interior region of the wafer is simply covered with thick and evenly deposited electrofill metal, which can be planarized by CMP down to the dielectric. This flat surface, which is mostly dielectric, is then covered with a barrier layer substance such as SiN, that both adheres well to the dielectric and aids in the adhesion of subsequent layers. Another reason to remove the residual PVD metal layers in the wafer edge area is that the barrier layers underneath them are also thin and uneven, which may allow migration of the metal into the dielectric. This problem is especially important when the metal is copper.
To address these problems, semiconductor equipment may have to allow etching of the unwanted residual metal layers. Various difficulties will be encountered in designing a suitable etching system.
One of the main difficulties involves the precise application of the etchant to the edge bevel region without allowing it to contact the active circuit region of the wafer. Physical shielding of the active circuit region is an option, but it is undesirable because contacting the wafer in this manner causes particle generation from the surface of the wafer. In addition, it is highly desirable to apply the etchant in a very narrow, confined region at the outer boundary of the wafer, so that the interior active circuit region is defined as expansively as possible. Other difficulties in designing an etching method and system include precise alignment of the wafer on the wafer chuck for rotation, proper pre-wetting, rinsing and drying procedures, and adequate clamping of the wafer in situations where undesired movement is possible. Since backside etching of the wafer is often necessary and desirable at the time of edge bevel removal (EBR), an invention addressing these needs should also be able to perform the back side etch.
Additional problems include the fact that etchant may splash back from the walls of the EBR module, thus causing unwanted oxidation (“streaking”) on the wafer surface. Nozzle orifices for dispensing the etchant are difficult to manufacture to precise desired diameters, and any variance in this diameter can result in significantly varying exit velocities from the nozzle. The taper from the region of metalization to the region without metal may also be quite wide, which is undesirable for purposes with respect to subsequent copper removal/planarization steps (e.g. CMP, electropolishing, electroetching).